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Communication Dans Un Congrès Année : 2021

An FPGA-based Emulation Platform for Edge Computing Node Design Exploration

Theo Soriano
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David Novo
Pascal Benoit

Résumé

Recent advances in machine learning have made it possible to consider the implementation of smart applications in constrained systems at the edge of the network. These memory and Central Processing Unit (CPU) intensive applications may require specific exploration methodologies to design efficient node computing devices. To better guide and validate these explorations, we need to perform energy and performance evaluations of the system. Software-based evaluation tools are applicationoriented and do not consider real-time and hardware constraints. Alternatively, hardware prototyping allows an accurate and realtime evaluation but offers limited flexibility and does not allow agile design exploration of the microcontroller unit (MCU). In this work, we propose a Field Programmable Gate Arrays (FPGA) based edge computing node emulation platform. Our solution combines the flexibility and the real-time capability of programmable logic with hardware prototype evaluation. We present an open-source microcontroller architecture for design exploration which integrates an activity monitor to collect traces at run-time. These activity traces are then used to profile the energy consumption of different components in the edge computing node. Importantly, our FPGA is connected to real sensors and communication modules to enable interactions with the environment during the node evaluation and exploration.

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Dates et versions

hal-03596105 , version 1 (03-03-2022)

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Theo Soriano, David Novo, Pascal Benoit. An FPGA-based Emulation Platform for Edge Computing Node Design Exploration. RSP 2021 - 32nd International Workshop on Rapid System Prototyping, Oct 2021, Virtual event, France. pp.8-14, ⟨10.1109/RSP53691.2021.9806230⟩. ⟨hal-03596105⟩
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