A CFI Verification System based on the RISC-V Instruction Trace Encoder - CMPGC / SAS : Systèmes et Architectures Sécurisées
Article Dans Une Revue Microprocessors and Microsystems: Embedded Hardware Design Année : 2023

A CFI Verification System based on the RISC-V Instruction Trace Encoder

Anthony Zgheib
Olivier Potin
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Jean-Max Dutertre

Résumé

Physical attacks are powerful threats that can cause changes in the execution behavior of a program. Control- Flow Integrity (CFI) is used to check the program’s flow execution, ensuring that it remains unaltered by these attacks. The RISC-V Trace Encoder (TE) provides valuable information about the user program’s execution path, and is used as part of a CFI solution. An enhanced version of the TE specifications permits detecting intricate fault models such as the corruption of any discontinuity instruction, using an additional Trace Verifier (TV) hardware module. In this paper, we present a buffer overflow software attack simulation and experimental ElectroMagnetic Fault Injection (EMFI) attacks conducted on an Field Programmable Gate Array (FPGA) board that implements a RISC-V core linked to the enhanced TE and TV modules. Unlike existing CFI solutions, our proposed approach does not require modifications to the RISC-V compiler, user application code or the RISC-V core. The average overhead of our solution in terms of hardware area, memory and power consumption are equal to 13.6%, 3.5% and 9% respectively.
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Dates et versions

hal-04667590 , version 1 (06-08-2024)

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Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre. A CFI Verification System based on the RISC-V Instruction Trace Encoder. Microprocessors and Microsystems: Embedded Hardware Design , 2023, 103, pp.104968. ⟨10.1016/j.micpro.2023.104968⟩. ⟨hal-04667590⟩
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