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New Strategies for Engineering Tensile Strained Si Layers for Novel n-Type MOSFET

Abstract : We report a novel approach for engineering tensely strained Si layers on a relaxed silicon germanium on insulator (SGOI) film using a combination of condensation, annealing, and epitaxy in conditions specifically chosen from elastic simulations. The study shows the remarkable role of the SiO2 buried oxide layer (BOX) on the elastic behavior of the system. We show that tensely strained Si can be engineered by using alternatively rigidity (at low temperature) and viscoelasticity (at high temperature) of the SiO2 substrate. In these conditions, we get a Si strained layer perfectly flat and free of defects on top of relaxed Si1–xGex. We found very specific annealing conditions to relax SGOI while keeping a homogeneous Ge concentration and an excellent thickness uniformity resulting from the viscoelasticity of SiO2 at this temperature, which would allow layer-by-layer matter redistribution. Remarkably, the Si layer epitaxially grown on relaxed SGOI remains fully strained with −0.85% tensile strain. The absence of strain sharing (between Si1–xGex and Si) is explained by the rigidity of the Si1–xGex/BOX interface at low temperature. Elastic simulations of the real system show that, because of the very specific elastic characteristics of SiO2, there are unique experimental conditions that both relax Si1–xGex and keep Si strained. Various epitaxial processes could be revisited in light of these new results. The generic and simple process implemented here meets all the requirements of the microelectronics industry and should be rapidly integrated in the fabrication lines of large multifinger 2.5 V n-type MOSFET on SOI used for RF-switch applications and for many other applications.
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Submitted on : Friday, January 15, 2021 - 9:38:13 AM
Last modification on : Saturday, January 16, 2021 - 3:31:05 AM


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Thomas David, Isabelle Berbezier, Jean-Noël Aqua, Marco Abbarchi, Antoine Ronda, et al.. New Strategies for Engineering Tensile Strained Si Layers for Novel n-Type MOSFET. ACS Applied Materials & Interfaces, Washington, D.C. : American Chemical Society, 2021, 13 (1), pp.1807-1817. ⟨10.1021/acsami.0c16563⟩. ⟨hal-03111073⟩



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