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Elaboration et intégration de nanofils GeSn pour la réalisation de dispositifs nanoélectroniques basse consommation

Abstract : Since the 1960's, technological development has been mainly driven by the miniaturization of components and follows the famous Moore's law. Indeed, miniaturization brought many advantages at the start. Lower switching time, more compact systems, lower supply voltage, and therefore, transistors consuming less, etc. However, this approach has started to falter in recent years. Indeed, the limits of miniaturization began to appear and the overall power consumption of the circuits began to increase which limits the realization of the systems. It then becomes necessary to develop low-consumption components, such as tunnel effect transistors. These transistors have, to date, a major defect which is their currents in the on state, much weaker than the MOSFETs. This current depends mainly on the architecture of the transistor as well as on the gap width of the source material.In this thesis, we propose to develop and study nanowires and heterostructures based on the germanium-tin alloy. The $ Ge_{1-x}Sn_x $ is an alloy of column IV which has a very small gap, less than 0.66 eV with the particularity of passing from an indirect gap to a direct gap from a concentration 10% of tin, which is favorable to tunnel effect transistors. Nanowires were developed by chemical vapor deposition using the vapor-liquid-solid mechanism and physicochemical analyzes such as X-ray spectroscopy and nano-Auger spectroscopy were used to characterize them. Hypotheses have been put forward in order to understand the mechanisms involved in the growth of GeSn nanowires and to better control their development. Axial heterostructures which will serve as basic materials for the realization of tunnel effect transistors are presented and detailed. We then present the study of the GeSn/dielectric interface in order to improve the performance of MOS capacities on GeSn, and therefore, to improve nanoelectronic devices. Chemical treatments were applied to the GeSn surface, and XPS and pAR-XPS analyzes were conducted to determine the effectiveness of the treatments. In order to improve the performance of the MOS capacities, we deposited a stack formed of an interfacial layer followed by a dielectric with high permittivity, such as $ HfO_2$, in order to obtain a low interface trap density. Finally, the integration and study of tunnel effect transistors based on heterostructures are presented. We first present the technological development stages developed in order to produce nanoelectronic devices. The doping levels of the heterostructures were evaluated by means of resistivity measurements. The performances of tunnel effect transistors were evaluated using electrical measurements and were compared with the current state of the art.
Keywords : GeSn Tunnel FET Mos
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Submitted on : Tuesday, December 15, 2020 - 12:31:14 PM
Last modification on : Tuesday, February 16, 2021 - 3:33:49 AM
Long-term archiving on: : Tuesday, March 16, 2021 - 7:25:07 PM


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  • HAL Id : tel-03066536, version 1



Thibault Haffner. Elaboration et intégration de nanofils GeSn pour la réalisation de dispositifs nanoélectroniques basse consommation. Micro et nanotechnologies/Microélectronique. Université Grenoble Alpes [2020-..], 2020. Français. ⟨NNT : 2020GRALT028⟩. ⟨tel-03066536⟩



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